IEEE 1241:2000 pdf free download

IEEE 1241:2000 pdf free download.IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters.
The type of circuitry used to capture the digital data samples produced by the ADC is deermined largely by the data rate, Slower ADCs may be interfaced directly to the computer. ADCs often require a butter memory to acquire data at the ADC sample rate and then download accumulated samples to the computer at a slower rate. Even faster ADCs may require latches andor de-multiplexers between the ADC and the buffer memory. and perhaps data decimation, as described in 41.2.1. A logic analyzer might be used as a buffer memory to capture data for some tests.
4.1.1 Test setup
A few general test setups can be used to perform most of the ADC tests presented in this standard. Test setups that use sine waves, arbitrary waveforms, and pulses are described in the following sub- clauses. Some tests, such as those for VSWR and out-of-range signals. require setups other than those discussed in the following subclauses.
4.1.1.1 Sine wave test setup
Figure 3 shows the sine wave test setup. Sine waves are commonly used in ADC testing because appropriate sine wave sources are readily available and because it is relatively easy to establish the quality of the sine wave (e.g., with a spectrum analyzer). A sine wave generator provides the test signal while a clock generator provides the clock (or conversion) signal. Also, combining the output of two (or three) sine wave generators can produce two-tone (or three-tone) test signals for intermodulation distortion testing. Additionally, a noise generator’s output can be combined with a signal to provide low-level dither (Gray and Stockham IBI I]).
If frequency synthesizers are used to generate the test and clock signals, the synthesizers can often be phase-locked to maintain precise phase relationships between the signal and the sampling clock. Phase-locking of synthesizers facilitates testing and simplifies subsequent digital signal processing. by preventing clocksignal walkthrough (beat patterns) that may artificially increase or reduce measured spurious output.
Both the clock and the test signals must be suitable for the test being performed. Filters may be required in either the clock or signal paths to reduce noise or harmonic distortion. For example,sub-harmonics in the clock path will degrade ADC performance,so the clock signal may requirefiltering to smooth edges which might otherwise feed through to the signal path. Also,low-pass orband-pass filters may be required in the signal path to eliminate noise or other undesirable signals (e.g.,harmonics).The relative jitter between the clock and test signals must be low enough to prevent jitterartifacts from affecting the measured noise floor as described in 4.5.2.5.